Silicon-on-insulator (SOI) structures comprise a buried insulating layer which electrically isolates a silicon layer from a silicon substrate. The SOI structure does not always occupy the entire surface of a silicon substrate; rather, the SOI structure sometimes occupies only a portion of the silicon substrate. The area assigned to the SOI structure is commonly referred to as the SOI region and the area outside the SOI structure is commonly referred to as the bulk region.
A semiconductor device having a bulk region and an SOI region has the advantages of excellent crystallization of the bulk region and excellent element insulation of the SOI region. For example, logic memory circuits are preferably formed in bulk element regions while high performance logic circuits are preferably formed in the SOI region. It is desirable, therefore, for a semiconductor device to have areas of SOI and bulk silicon adjacent on the same wafer.
Numerous techniques have been developed to form SOI and bulk regions. One of the most manufacturable techniques is ion implantation which involves the implantation of high energy ions into a solid surface to form a buried layer. Because the implanted dopants are generally not in the proper lattice position and are mostly inactive, a high temperature annealing process is often used to repair crystal damage and electrically activate the dopants. Implantation of oxygen into silicon is generally a preferred process for building SOI substrates. The separation by implanted oxygen (SIMOX) process can be used, for example, in very large scale integration (VLSI) devices.
Unfortunately, masked or patterned ion implantation produces a region of partial implantation, referred to as the transition region, in the semiconductor substrate. The transition region forms between the area that receives the full ion implant dose and the region that was shielded from implantation, known as the mask region. As a result of this partial dose, the transition region is highly defective, containing crystal defects that may propagate to other regions of the semiconductor silicon layer.
U.S. Pat. No. 5,740,099 issued to Tanigawa teaches building areas of SOI and bulk silicon wafers on a substrate and building different types of circuits in each area. Tanigawa discusses the concept of making multiple regions of SOI and bulk, on the same wafer, using a patterned ion implant. This method is known to cause defects at all of the patterned edge regions. Tanigawa fails to address this defect region and presumably just spaces the devices so that no transistor falls within the transition defect region.
U.S. Pat. No. 5,612,246 issued to Ahn describes a method and structure in which standard SIMOX SOI wafers are patterned and then the silicon and buried oxide are etched down to the bulk silicon substrate. Ahn then builds devices on the bulk silicon substrate. One problem with this method is that the structure is non-planar and, therefore, the levels or heights of the bulk and SOI devices are different on the wafer. Consequently, every film that is deposited and etched will leave a side wall or rail around the step between the two levels of silicon.
U.S. Pat. No. 5,364,800 and U.S. Pat. No. 5,548,149, both issued to Joyner, teach a technique using masking oxide of various thickness to produce a buried oxide layer of differing depths. At the extreme ends of the ranges of the mask thickness, Joyner can create thick SOI, thin SOI, or bulk silicon regions. Thus, Joyner can create a substrate with both SOI and bulk regions. Although he uses a patterned implant to form SOI and bulk regions, Joyner does not in any way address the transition region where the buried implant ends and the bulk silicon begins.
U.S. Pat. No. 4,889,829 issued to Kawai describes a method of making bulk and SOI regions on the same substrate. Kawai builds the bulk in the original substrate and then deposits, using chemical vapor deposition or CVD, an oxide on top to form the buried oxide. Silicon (polysilicon) is then deposited on top of the oxide. Because high-quality devices cannot be built on polysilicon, Kawai then recrystallizes the poly with a laser to form a single crystal. SOI devices are then built on this layer. The final structure is non-planar, as is the structure taught by Ahn, with the inherent problems of such a structure. In addition, the process described by Kawai is impractical because control over recrystallization of the poly is poor.
U.S. Pat. No. 5,143,862 issued to Moslehi teaches SOI wafer fabrication by selective epitaxial growth. Moslehi etches wide trenches, deposits a buried oxide by CVD, removes the oxide from the side walls of the trench, then uses selective epitaxial growth to grow the silicon over the oxide region. Moslehi then isolates the region by forming side walls on the epitaxial mask, continues to grow the silicon to the surface, and, finally, removes the side walls and etches a trench filled with dielectric to isolate devices. The method does not remove the damage regions in the transition phase. In fact, the trench does not extend past the buried oxide layer.
Japanese Patent No. 06334147 issued to Hitachi Ltd. teaches dividing a substrate into areas of SOI and bulk and placing different circuit types in each region to obtain specific advantages for each region. Because stacked capacitors are raised above the bulk silicon surface, SOI regions are created that are raised such that the final chip is planar with respect to all regions. It appears that the top silicon and buried oxide are removed from the SOI structure to leave bulk substrate regions for memory cells. Thus, the structure is a mixed substrate with memory on bulk and SOI for logic and an approximately planar surface.
U.S. Pat. No. 5,399,507 issued to Sun also describes a method and structure for forming bulk and SOI regions on a single substrate. The method starts with blanket SOI (formed by SIMOX) and then etches away the silicon and buried substrate layer down to the silicon substrate. At this step of the method, the structure is similar to the structure disclosed by Ahn in that the structure has an exposed bulk silicon region at a different level than the top of the SOI region. Sun goes further, however, and places a side wall on the etched opening then uses selective epitaxial growth on the silicon which is a continuation of the single crystal silicon. The epitaxial growth continues up to the surface of the SOI region so that the region is planar. Sun may also use a planarizing step to ensure that the two regions are on the same plane. Sun fails either to improve the patterned implants or to remove any defect regions which may exist. The patterned SOI implant taught by Sun in an alternate embodiment does not have any isolation, nor does Sun indicate that any isolation is necessary. Moreover, there is no way to self-align an isolation with the mask structure.
The deficiencies of the ion implantation processes of building SOI substrates show that a need still exists for eliminating the highly defective transition area that receives a partial dose of ion implant. To overcome the shortcomings of ion implantation processes, a new process is provided. An object of the present invention is to provide a process of forming patterned SOI layers without forming a highly defective transition region.